The implementation of CDR (Clock Data Recovery) is a key to high speed I/O interfaces such as high speed asynchronous serial buses. FIG. 1 is a functional block diagram illustrating a portion of a Phase Locked Loop (PLL) based CDR circuit. The circuit shown in FIG. 1 includes a phase/frequency detector 11 which, in a frequency mode, outputs an up/down pulse signal according to the phase/frequency difference between a local reference clock ref-clock and a clock signal Ck generated by a voltage controlled oscillator (VCO) 16. When the frequency of the local reference clock ref-clock is higher than that of the clock signal Ck, an up pulse signal is outputted by the phase/frequency detector 11. On the contrary, if the frequency of the local reference clock is lower than that of the clock signal Ck, a down pulse signal is outputted. The up/down pulse signal is then processed by a charge pump 14 and a loop filter 15 and inputted to the VCO 16 as a control voltage of the last order VCO 16. Accordingly, the frequency of the clock signal Ck outputted by the VCO 16 can be adjusted to approximate to the frequency of the local reference clock ref-clock. With the feedback of the resulting clock signal Ck to the phase/frequency detector 11, the frequency of the clock signal Ck can approximate to the local reference clock ref-clock to a certain extent, and then the multiplexer 13 is switched into a phase mode to have the received data Rdata sampled with the adjusted clock signal Ck.
The CDR circuit further includes a phase detector 12 for detecting the phase difference between the received data Rdata and the adjusted clock signal Ck as it is infeasible to define a sampling frequency according to the waveform of the high speed asynchronous serial data Rdata. The phase difference is then referred to adjust the phase of the clock signal Ck, thereby stably locking data for data recovery. However, the differentiation of the frequencies of the data Rdata and the reference clock signal would be inevitable or unpredictable if different clock sources are used in respective interfaces or low frequency power/ground noises occur between interfaces. If the frequency difference is beyond a certain level, there would be problem in locking data in the phase mode. Generally, a minor data-locking problem can be solved by accelerating the response of the PLL circuit. However, the data-locking problem resulting from significant frequency difference cannot be simply solved in this way because the ability of the conventional phase detector to track the frequency variation is limited.